1. Field of the Invention
This invention relates to a junction-field-effect transistor (JFET) with a self-aligned p type gate and a method of producing it.
2. Discussion of Background
JFETs with a GaAs substrate are well-known. FIG. 1 is the cross-sectional view of a typical configuration of the gate of such JFETs. On a semi-insulating GaAs substrate 1 is formed an n type active layer 3 in which a p type gate 5 is formed. A source and a drain 7, 9 are formed in the GaAs substrate 1 and the n type active layer 3. An insulating film 11, having contact holes on the gate 5, source and drain 7, 9 is formed on the n type active layer 3. A gate electrode 13 is formed on the gate 5 in such a manner that it contacts the gate 5 through the contact hole and partially overlaps the insulating film 11. A source electrode and a drain electrode 15, 17 are formed on the source and drain 7, 9.
A GaAs JFET with the configuration as shown in FIG. 1 can be produced by, for example, the following steps disclosed in the article "GaAs JFET Formed by Localized Zn Diffusion" in "IEEE ELECTRON DEVICE LETTERS, VOL. EDL-2, NO. 7, JULY."
First, the n type active layer 3 is formed on the semi-insulating GaAs substrate 1 by ion implantation. The source and drain 7, 9 are formed. The insulating film 11 is formed to cover the surfaces of the n type active layer 11 and the source and drain 7, 9. A contact hole is formed by, for example, photolithography in that portion of the film 11 under which a gate is to be formed. A high heat treatment is performed in metal vapor containing an acceptor impurity such as zinc (Zn). This diffuses the zinc into the n type active layer 3, forming the p type gate 5. The gate electrode 13 and source and drain electrodes 15, 17 are formed.
But, this method makes it difficult to control the compositions of the metal vapor, temperature, vapor flowing speed, etc. In particular, in order to suppress the discompose of arsenic contained in the GaAs substrate 1, the method requires that the arsenic be contained in the metal vapor. It is, however, extremely difficult to control the ratio of the arsenic in the metal vapor. This will not provide the gate 5 with a uniform depth (depth of a pn junction). Naturally, GaAs JFETs produced by the conventional method do not have good reproducibility characteristics. Particularly, the conventional method provides poor characteristic reproducibility for enhancement type GaAs JFETs, which require, finely controlled the junction depth of the gate 5 in the order of 0.1 .mu.m.
To overcome the drawbacks of the aforementioned method, there has been proposed a GaAs JFET-producing method disclosed in, for example, Electronics Letters, Vol. 17, No. 17, pp. 621-623 entitled "Fully Ion-Implanted GaAs ICs Using Normally-Off JFETs" by J. Kasahara et al. According to this method, Zn ions are implanted in the n type active layer 3 with the insulating film 11 used as a mask and then the resulting structure is heat-treated, thus forming the p type gate 5. The second conventional method also gives rise to zinc diffusion by heat-treatment; therefore, it is very difficult to control the formation of a shallow pn junction.
Considering its characteristic, the JFET should desirably have a thin gate. However, the thinner the gate 5, the greater the gate resistance. In order to reduce the gate resistance, therefore, it has been necessary to form a metal film (gate electrode 13) on the gate 5. Both of the discussed methods form the gate electrode 13 by photolithography. Because this process needs some allowance for mask alignment, the gate electrode 13 partially overlaps the insulating film 11 as shown in FIG. 1. Consequently, a parasitic capacitance is produced between the gate electrode 13 and the n type active layer 3 and source and drain 7, 9 through the insulating film 11, reducing the operation speed of the JFET. In addition, as described above, the conventional methods should form the gate electrode 13, made of metal, after forming the gate 5, thus requiring an additional step.
In the field of MOSFETs, as disclosed in the Japanese Patent Disclosure (Kokai) No. 53-105984, there has been proposed a technique of improving a transconductance by providing a thin, high impurity p type layer under a gate electrode.